This invention relates to a phase comparison and error correction circuit, and more particularly, to a correction circuit which utilizes a biasing scheme to minimize diode leakage current, and therefore variation of the output control voltage.
Referring to FIG. 1, there is shown a prior art phase comparison and error correction circuit 10. Circuit 10 comprises an emitter-coupled logic (ECL) phase detector 12 and a correction circuit 14. The ECL phase detector 12, which is biased between ground and -5.2 volts, receives two signals Ph.sub.1 and Ph.sub.2. Typically, the purpose of circuit 10 is to maintain alignment (synchronization) between Ph.sub.1 and Ph.sub.2. However, depending on different applications, such as frequency modulation, Ph.sub.1 and Ph.sub.2 might lose their synchronicity.
ECL phase detector 12 is responsible for detecting whether Ph.sub.1 and Ph.sub.2 are out of phase, and if so which one is ahead of the other. If Ph.sub.1 is ahead of Ph.sub.2, the ECL phase detector 12 sends out a pulse on its error output 16 and if Ph.sub.2 is ahead of Ph.sub.1, the ECL phase detector 12 sends out a pulse on its error output 18. Finally, if the two signals Ph.sub.1 and Ph.sub.2 are in synch with each other, the ECL phase detector 12 sends out substantially equal pulses on outputs 16 and 18.
As shown on output 16, the pulse sent out by the ECL phase detector 12 is a negative pulse which has a transition from about -0.9 volts to about -1.7 volts and back to -0.9 volts. The width of the error pulse depends on how far the phases of Ph.sub.1 and Ph.sub.2 are from each other. Typically, the width of the error pulse is in the range of nanoseconds or picoseconds. The error pulse on output 18 has the same voltage characteristics as those of the error pulse on output 16, except it is generated only when Ph.sub.2 is ahead of Ph.sub.1.
Correction circuit 14, which receives an error pulse either from output 16 or output 18, generates a corresponding correction signal at the output node 20 to be used to align Ph.sub.1 and Ph.sub.2 signals. The outputs 16 and 18 are connected to nodes 22 and 24 of the correction circuit 14 respectively. Nodes 22 and 24 are connected to -5.2 volts through resistors R.sub.11 and R.sub.12 respectively. The output of Op-amp 26, the correction signal, is connected to the output node 20. The inverting input (-) of the Op-amp 26 is connected to the anode of a diode D.sub.11 and the cathode of diode D.sub.11 is connected to node 22 through resistor R.sub.13. The non-inverting input (+) of the Op-amp 26 is connected to the anode of a diode D.sub.12 and the cathode of diode D.sub.12 is connected to node 24 through resistor R.sub.14. The inverting input of Op-amp 26 is also connected to node 20 through a capacitor C.sub.11 and the non-inverting input of Op-amp 26 is grounded through capacitor C.sub.12.
In operation, nodes 22 and 24 are kept at near -0.9 volts through the outputs 16 and 18 respectively unless they receive an error pulse. In the absence of an error pulse, the inverting and non-inverting inputs of the Op-amp 26 are substantially at the same voltage.
An error pulse on output 16 causes the voltage of node 22 to drop to about -1.7 volts. The voltage of node 22 drops and causes a forward bias across D.sub.11. This will draw current from capacitor C.sub.11 through resistors R.sub.13 and R.sub.11 which causes the capacitor C.sub.11 to discharge. As capacitor C.sub.11 starts discharging, the voltage of the inverting input of the Op-amp 26 drops. However, the voltage of the non-inverting input of the Op-amp 26 stays constant. The lower voltage on the inverting input compared to the voltage of non-inverting input of the Op-amp 26, causes the output voltage of the Op-amp 26 to increase. Therefore, when Ph.sub.1 is ahead of Ph.sub.2, the voltage of the correction signal is increased. Once the error pulse ends, the voltage of node 22 returns to about -0.9 volts and C.sub.11 will stop discharging. This will cause the value of the correction signal to stay at its new level. Typically, if no correction is required, the normal level of correction signal depends on the system in which the correction circuit is used.
A similar phenomenon happens when the output 18 delivers an error pulse to the correction circuit 14. This will cause a forward bias across diode D.sub.12 and draws current through R.sub.14 and R.sub.12 which results in discharging capacitor C.sub.12. Once capacitor C.sub.12 starts discharging, the voltage of the non-inverting input of the Op-amp drops while the voltage of the non-inverting stays constant. This causes a voltage difference between the two inputs of the Op-amp 26 which results in lowering the correction signal. Therefore, if Ph.sub.2 is ahead of Ph.sub.1, the voltage of the correction signal will be lowered. The amount by which the voltage of the correction signal is lowered depends on the width of the error pulse. When the error pulse ends, the voltage of node 24 returns to about -0.9 volts and diode D.sub.12 returns to no bias, which stops discharging capacitor C.sub.12. As a result, the voltage of the correction signal stays at its new level.
In the absence of an error pulse, if the diodes D.sub.11 and D.sub.12 have any leakage current, they will cause the capacitors C.sub.11 and C.sub.12 to slightly charge or discharge respectively. Such leakage current will cause the voltage at the inputs of the Op-amp 26 to change and therefore change the output voltage (correction signal). This is an undesirable effect which can cause an unwanted phase change between Ph.sub.1 and Ph.sub.2. It should be noted that the leakage current is usually not enough to change the voltages at nodes 22 and 24. However, the charge/discharge of either capacitor C.sub.11 or the capacitor C.sub.12 is enough to create a voltage difference at the inputs of the Op-amp 26 and change the correction signal. This phenomenon is magnified as the temperature increases since the leakage current of diodes increases exponentially as the temperature rises.
In FIG. 1, a reference voltage V.sub.REF (biasing voltage) is connected to the inverting and non-inverting inputs of the Op-amp 26 through resistors R.sub.14 and R.sub.15 respectively. V.sub.REF is a -0.9 volts, temperature stable and regulated voltage which is selected to match the voltages of the outputs 16 and 18. The purpose of using a biasing voltage V.sub.REF is to keep the voltage of the inverting and non-inverting inputs of the Op-amp 26 at a level that minimizes leakage current in diodes D.sub.11 and D.sub.12. This in turn causes the output voltage of the Op-amp 26 to stay at a fixed level regardless of the leakage current unless an error pulse is generated.
This kind of bias is not effective. The problem arises due to different tolerance ranges of the different outputs of the ECL phase detector 26. Each output of the ECL phase detector 26 has a different tolerance range and each tolerance range changes as the temperature changes. Typically, a biasing voltage V.sub.REF is selected to be in the middle of tolerance ranges to match voltages at outputs 16 and 18. However, as the temperature changes, the tolerance ranges change, but the temperature insensitive biasing voltage stays constant. Therefore, as the temperature changes, the biasing voltage V.sub.REF no longer matches the voltages at the ECL outputs 16 and 18. A voltage difference between the biasing voltage V.sub.REF and the ECL outputs 16 and 18 causes the leakage currents to change the input voltages of the Op-amp 26.
It is an object of this invention to provide a biasing scheme to minimize the undesirable effects of diode leakage current on the phase comparison and error correction circuit and provide a substantially fixed correction signal in the absence of an error pulse.